The hardware description language for this free IP core is Verilog.
Features:
- Implements the 802.3 specifiction.
- Half-duplex support for 10 100 Mbps mode
- FIFO interface to user application
- Supports pause frame generation and termination
- Transmitting frames source MAC address insertion
- Receiving frames destination MAC address filter
- Receiving broadcast frames throughout constraint
- Supports Jumbo frames 9.6K
- RMON MIB statistic counter
Project name:
ethernet_tri_mode
