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Cswitch - Configurable Switch Array for highspeed networking

 
Post new topic   Reply to topic    NG Ethernet Forum -> 100 Gigabit Ethernet (100GE) -> 100G Ethernet (100GE) Chips and Components
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knoll
NGE rank 90
NGE rank 90


Joined: 11 Apr 2006
Posts: 98
Location: Germany

PostPosted: Fri Apr 13, 2007 3:42 pm    Post subject: Cswitch - Configurable Switch Array for highspeed networking Reply with quote


The Cswitch Corporation from Santa Clara offers a very interesting chip specifically designed to provide all necessary switch components in a configurable - FPGA like - manner.
Quote:
With all the Configurable Switch Array has to offer,
designers can now replace both costly and timeconsuming ASICs, and slow, inadequate FPGAs with a chip that offers the best of both.

This "2 GHz switch specific FPGA" for networking provides the following resources internally:

  • Configurable MACs:
    - 10/100/1000 Mbps Ethernet
    - 10 Gbps Ethernet
    - 1/2/4 Gbps Fibre Channel
  • SERDES:
    - 4 Lane 1–6.4 Gbps full duplex
    - Serial Links for 1 Gbps Ethernet,
    - 10 Gbps XAUI, Fibre Channel
    - PCI Express
    Programmable Logic Blocks (PLBs):
    - Up to 500 MHz FPGA Logic (4 Input LUTs with 64 Bits of Distributed RAM)
  • Dual Port RAMs:
    - 1 GHz SRAMs, up to 2.2 Mb
  • PacketParser™ Frame Parser Blocks:
    - 800 MHz Nanoprocessors for parsing layer 2–4 protocols such as Ethernet, TCP/IP, MPLS, and Fibre Channel
  • Reconfigurable Arithmetic Units (RAUs):
    - 1 GHz Reconfigurable Arithmetic Units for packet editing (CRC, hashing, checksums, etc.)
  • Reconfigurable CAMs (RCAMs):
    - 1 GHz Reconfigurable CAMs for packet classification and filtering
  • Single Port RAM:
    - 1 GHz SRAM storage,up to 16 Mb

The chip is suitable for up to 100 Gbit networking applications. Internally, it relies on a 20-bit wide 2 GHz bus with Cswitchs own dataCrossconnect™ intersections.
Quote:
It’s the first configurable solution to deliver bandwidth at 40 to 100 Gbps for a range of applications, making it capable of moving up to 6 TBps of packets at speeds of up to 2 GHz. To handle editing tasks, the chip packs a rich
assortment of Frame Header Parsers, Arithmetic Units, and RCAMs to edit and classify packets at 1 GHz speeds. For storing packets, the chip includes over 18 Mb of on-chip memory, as well as support for the latest high-speed memories, such as DDR2, RLDRAM2, and QDR2.

For further information, please get in contact with
Cswitch Corporation.
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